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The conversation around mobile AI has been dominated by talk of NPUs, TPUs, and dedicated neural accelerators. But what if your phone’s general-purpose CPU could shoulder that burden instead? Arm is betting big on exactly that with its new C2-Ultra, the powerhouse architecture set to define the next generation of 2027 flagships — from the latest MediaTek and Samsung silicon to, perhaps, Google’s future Tensor chipsets.
Arm’s pivot here is interesting, if that’s the right word. Shifting focus away from just pushing higher clock speeds and pipeline width towards accelerating more specialist use cases has potentially significant upsides if those workloads stick around. However, there’s no guarantee the market won’t keep demanding ever-higher peak general performance, particularly as mobile and PC use cases continue to collide.
So let’s dig into this year’s C2-Ultra, -Premium, -Pro, and -Nano CPU cores to see what this revised strategy entails.
The headline CPU announcement from Arm this year is the C2-Ultra, the powerhouse successor to last year’s C1-Ultra. While Arm does not confirm partner products ahead of time, the usual cadence of silicon releases means this new core is likely headed to next-gen Samsung Exynos and MediaTek Dimensity chipsets for phones around the turn of 2027. We might even see it in Google’s next-gen Tensor G7 , if we’re lucky.
For headline figures, Arm says the core boasts up to 15% improved peak performance over its predecessor. However, a clock speed boost to a rather speedy 4.45GHz accounts for 8% of the performance improvements, so only the remaining 7% comes from core architecture improvements. Perhaps more importantly, the core can deliver the same performance as last year’s model while reducing power consumption by 38%, thanks in no small part to the move to 2nm. C2-Ultra can now have up to 3 MB of L2 cache, a useful performance upgrade for processors willing to trade silicon area for memory.
What’s interesting, and perhaps a little unusual for Arm, the C2-Ultra pipeline is the same width as the C1-Ultra. The performance improvements aren’t coming from doing more work with each clock cycle. Instead, Arm has boosted the C2-Ultra’s execution window by 30%, meaning there are around 2600 instructions in flight at any one time, compared to 2000 in C1-Ultra. Likewise, Arm has beefed up its out-of-order execution mechanisms with smarter speculation and faster recovery, enabling earlier detection and execution of code dependencies by analyzing the workload and data types.
The general idea is that the C2-Ultra spends less time waiting for data and, where possible, selects important code to run in the optimal order. Removing these bottlenecks slightly speeds up execution and reduces power consumption by reducing the time spent moving data between caches.